1. Field of the Invention
This invention relates to the field of semiconductor processing and, more particularly, to a method of forming a shallow trench isolation structure with a protective nitride layer formed upon the upper surface of the trench dielectric oxide.
2. Description of Relevant Art
The fabrication of an integrated circuit involves placing numerous devices on a single semiconductor substrate. Isolation structures are needed to electrically isolate one device from another. Isolation structures define the field regions of the semiconductor substrate and the device areas define the active regions. The devices are interconnected with conducting lines running over the isolation structures.
A popular isolation technology used in integrated circuits involves the process of locally oxidizing silicon. Local oxidation of silicon, or LOCOS process, involves oxidizing field regions between device active regions. The oxide grown in field regions is termed field oxide. Field oxide is grown during the initial stages of integrated circuit fabrication before the gate conductor and source/drain regions are formed in active areas. By growing a thick field oxide in isolation (or field) regions pre-implanted with a channel-stop dopant, LOCOS processing serves to prevent the establishment of parasitic channels in the field regions.
While LOCOS has remained a popular isolation technology, there are several problems inherent to LOCOS. First, a growing field oxide extends entirely across the field region and laterally as a bird's beak. In many instances, the bird's beak can unacceptably encroach into the device active area. Second, the pre-implanted channel-stop dopant often redistributes during the high temperatures associated with field oxide growth. Redistribution of channel-stop dopant primarily affects the active area periphery causing problems known as narrow-width effects. Third, the thickness of field oxide causes large elevational disparities across the semiconductor topography between field and active regions. Topological disparities cause planarity problems which become severe as circuit critical dimensions shrink. Lastly, thermal oxide growth is significantly thinner in small field (i.e., field areas of small lateral dimension) regions relative to large field regions. In small field regions, a phenomenon known as field-oxide-thinning effect therefore occurs.
Many of the problems associated with LOCOS technology are alleviated by an isolation technique known as shallow trench isolation ("STI"). Despite advances made to decrease bird's-beak, channel-stop encroachment and non-planarity, it appears that LOCOS technology is still inadequate for deep submicron technologies. The shallow trench process, herein "trench process", is better suited for isolating densely spaced active devices having field regions less than, e.g., 3.0-5.0 .mu.m in the lateral dimension. Narrow width STIs may be used to isolate densely spaced devices and larger width STIs may be used to isolate devices that are spaced further apart.
The trench process involves the steps of etching a silicon substrate surface to a relatively shallow depth, e.g., between 0.2 to 0.5 microns, and then filling the shallow trench with a deposited dielectric (referred to henceforth as "trench dielectric"). Some trench processes include an interim step of growing oxide on the trench walls prior to filling the trench with the dielectric. The trench dielectric may comprise decomposed tetra-ethyl-ortho-silicate ("TEOS") deposited using a chemical-vapor deposition ("CVD") process. CVD may, for example, be performed at approximately 400-800.degree. C. in an atmospheric pressure or low-pressure chamber.
Exemplary shallow trench structures are shown in FIG. 1. Semiconductor substrate 10 is typically a single-crystalline silicon doped n-type or p-type. Shallow trenches 24 and 26 are etched into field regions 16 and 20 of semiconductor substrate 10. A trench dielectric such as TEOS may be used to fill the trenches. A thin layer of gate oxide 28 is thermally grown upon upper surface 12 of semiconductor substrate 10 and, to a lesser thickness, upon the trench dielectric. A layer of polysilicon is deposited upon gate oxide 28 and then patterned to form conductive structures 30, 32, and 34. Conductive structure 32 formed in active region 18 is used to align source and drain junction areas of a subsequently formed transistor. Conductive structures 30 and 34 are formed in field regions 16 and 20 and above shallow trenches 24 and 26. Conductive structures 30 and 34 may be used as conductive lines running over the field regions to interconnect devices in the active regions with one another.
During the etch process to pattern the polysilicon, possible damage to the trench dielectric may occur. Since it is very difficult to determine the exact end-point for the etch, the etchant may attack areas 36, 38, 40, and 42 and remove a portion of the trench dielectric to expose the corners and part of the sidewall surfaces of active areas adjacent shallow trenches 24 and 26. Damage to the corners of the shallow trenches not only degrades the isolation capabilities of the shallow trenches but, more importantly, reduces the transistor gate within the active areas beyond acceptable design levels.
As shown in FIG. 2, possible trench dielectric damage may also occur during oxide spacer formation. In processing steps subsequent to forming the polysilicon gate, a conformal oxide layer is deposited, preferably using CVD, upon the semiconductor topography and then anisotropically etched. An anisotropic etch removes material faster along horizontal surfaces than vertical surfaces. As a result, oxide spacers 44, 46, 48, 50, 52, and 54 are formed. The spacers are formed upon the sidewall surfaces of the conductive structures for various reasons, including: protecting the edges of the conductive structures from damage due to subsequent processing such as cleaning and etching; enabling self-aligned source/drain implants; and enabling self-aligned silicide formation.
During the anisotropic etch process, a portion of the trench dielectric in areas 36, 38, 40, and 42 may be undesirably removed. A typical subsequent processing step is the formation of silicide upon the conductive structures and upon the source/drain regions in the active areas. Silicide is formed upon exposed silicon to decrease the ohmic resistance between the silicon and subsequently deposited metal. Since the level of the trench dielectric due to damage from etching is now below upper surface 12 of semiconductor substrate 10, silicide will also form along the exposed silicon-based trench sidewalls. If areas 36, 38, 40, and 42 extend beneath the source/drain edge, the silicide will establish an undesirable electrical short between itself and the substrate (i.e., channel). Such a short would render the device non-functional. It would thus again be desirable to protect the upper surface of the trench dielectric against damage from etching during spacer formation.
Turning now to FIG. 3, in subsequent processing steps, interlevel dielectric 60 is deposited upon the semiconductor topography. Interlevel dielectric 60 electrically isolates the devices formed upon the semiconductor substrate from overlying conductive lines. To establish electrical contact between the overlying conductive lines and the polysilicon conductive structures 30, 32, and 34, a contact hole, such as hole 62, is first etched into interlevel dielectric 60. Metal is subsequently deposited into contact hole 62 in order to establish the electrical connection. Preferably, the contact is formed such that the deposited metal contacts only the upper surface of conductive structure 30. However, in case of a small misalignment, contact hole 62 may be displaced by a small amount. If hole 62 is displaced far enough, a portion of the deposited metal may contact the trench dielectric of trench 24 with the possibility of the metal spiking through the dielectric. If the metal spikes through a long enough distance, either vertically through the trench floor or horizontally through the trench sidewalls, an undesirable electrical short may be established between the semiconductor substrate and the deposited metal. Such a short would again render the device non-finctional. For at least the same reasons as before, it would be desirable to be able to protect the upper surface of the trench dielectric and prevent the deposited metal from penetrating into the trench dielectric and contacting the substrate edge beneath the source/drain area.
The trench dielectric is susceptible to damage throughout the production process. As well as during other processing steps, the trench dielectric can be damaged during: (i) etching for the purpose of patterning the polysilicon conductive structures; (ii) etching for the purpose of forming spacers upon the sidewall surfaces of the conductive structures; and, (iii) etching a misaligned contact hole and depositing metal into it for the purpose of establishing contact to the conductive gate structures and/or source/drain junctions. It would thus be desirable to be able to protect the upper surface of the trench dielectric from etchants and other materials that might penetrate through the trench dielectric and cause damage.